1. Field of the Invention
The present invention relates to the field of microelectronics fabrication. More specifically, the present invention relates to the forming of dielectric layers as insulation for semiconductor microelectronics devices.
2. Description of the Related Art
In the fabrication of semiconductor microelectronics devices employed in modern integrated circuits, it has become critical to reduce the various dimensions of the devices in order to improve performance and reduce cost. In particular, the metal-oxide-silicon (MOS) field-effect transistor (FET) device type has become one of the most important classes of integrated circuits. These MOSFET-type circuits are employed where the greatest circuit density and lowest power dissipation are needed. In order to achieve the utmost advantage of this particular type of device, it is desirable to minimize the dielectric thickness of the gate insulation (xe2x80x9coxidexe2x80x9d portion of the MOS structure) over the conductive channel of the device. It has become customary to employ extremely thin layers of silicon oxide formed on silicon to provide this pate insulation, because the thermal oxidation of silicon in appropriate oxidizing ambient environents can be precisely controlled to produce the very thin silicon oxide dielectric layer desired, and additionally to permit the control of the electronics states and electrical charge at the interface between the silicon and the silicon oxide layer.
While layers of silicon oxide as thin as 30-40 angstroms may be utilized for the gate insulation, the reliability and manufacturability of the devices begins to be degraded below this thickness. There are many methods which have been employed to alleviate this natural limit while retaining the advantage of the thermally-grown oxide-silicon. It is the capacitance of the gate insulating layer which actually determines the performance of the MOS device, and the higher capacitance desired could be obtained by a higher dielectric constant material than silicon oxide, which is fairly low at K=3.9. However, attempts to replace silicon oxide directly with a higher dielectric constant material such as, e.g., silicon nitride (K=5.0) have not succeeded due to the difficulty of controlling the interface between the deposited insulator compared with the ease of control of the interface when it is a thermally grown silicon oxide layer. Therefore, many attempts have also been made to employ a composite gate insulator layer consisting of a thermally grown silicon oxide layer on the silicon substrate and a subsequently formed dielectric layer, usually of a higher dielectric constant material.
It is thus towards the goal of forming a gate insulating layer of a MOS device on a silicon substrate with a higher dielectric constant as well as the performance, reliability and manufacturability of thermally grown silicon oxide dielectric layers that the present invention is generally directed.
Various methods have been proposed for forming composite gate insulation dielectric layers on MOS devices, with higher K values than thermally grown silicon oxide dielectric layers.
For example, Tseng et al., in U.S. Pat. No. 5,712,208, disclose a method for forming a high-K dielectric layer on a substrate. The dielectric layer is a composite layer formed of a thin underlying layer with a substantial composition of nitrogen and fluorine, followed by a thermal oxide layer and an overlying deposited dielectric layer. An optional thermal heat cycle may be employed to densify the deposited dielectric layer.
Further, Gilmer et al., in U.S. Pat. No. 5,821,172, disclose a method for forming a silicon oxynitride dielectric layer on a single crystal silicon substrate. The method employs a first first thermal treatment in a N2 or argon atmosphere at between 400 and 700 degrees centigrade, followed by exposure to NH3 combined with either NO or N2O at 600 to 1100 degrees centigrade to form an oxynitride layer.
Still further, Doyle et al., in U.S. Pat. No. 5,891,798, disclose a method for forming a composite dielectric layer with a high dielectric constant on silicon. The method employs nitrogen implantation into silicon through a sacrifical surface layer of silicon oxide. After annealing and stripping the sacrificial silicon oxide layer, a high dielectric constant material such as a paraelectric material is deposited on the substrate.
Finally, Brady et al., in U.S. Pat. No. 5,940,736, disclose a method for forming a gate dielectric layer of silicon oxynitride on a silicon semiconductor substrate. The method employs a three-step process of growing, depositing and growing silicon oxide under low pressure (0.2 to 10 torr). At each step, N2O or NO may be employed in the oxidizing gas for light nitrogen incorporation and formation of silicon oxynitride from the silicon oxide dielectric layer.
Desirable in the field of microelectronics fabrication of MOS devices are additional methods for forming gate insulating layers with the properties of high dielectric constant combined with high performance, reliability and manufacturability.
It is towards these goals that the present invention is generally and specifically directed.
A first object of the present invention is to provide a method for forming upon a semiconductor substrate employed within a microelectronics fabrication a layer of dielectric material comprising a thermally grown silicon oxide layer and a high-K dielectric material.
A second object of the present invention is to provide a method in accord with the first object of the present invention, where the layer of dielectric material is a gate insulation layer of a MOS device formed employing a plasma method to convert part of the silicon oxide to a silicon nitride dielectric layer to provide a composite dielectric layer equivalent dielectrically to the original silicon oxide dielectric layer.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, where the composite gate dielectric materials of the gate insulating layer of a MOS device have the desirable performance, reliability and manufacturability of MOS devices employing thermally grown silicon oxide dielectric layers as gate insulation.
A fourth object of the present invention is to provide a method in accord with the first object of the present invention, the second object of the present invention, and/or the third object of the present invention, where the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided a method for forming, upon a semiconductor substrate employed within a microelectronics fabrication, a composite dielectric layer comprising a thermally grown silicon oxide dielectric layer and a subsequently formed high-K dielectric layer. To practice the invention, there is first provided a silicon semiconductor substrate. There is then formed upon the silicon semiconductor substrate a silicon oxide dielectric layer employing a thermal oxidation method. There is then formed upon and partly into the silicon oxide dielectric layer a layer of silicon nitride employing a plasma deposition method to convent some of the silicon oxide to silicon nitride and retain the total dielectric thickness of the original silicon oxide dielectric layer. A subsequent layer of optional additional high-K dielectric material may then be deposited over the composite silicon oxide-silicon nitride dielectric layer if additional capacitance is desired.
The present invention provides a method for forming a composite gate insulating dielectric layer upon a semiconductor silicon substrate with an equivalent dielectric thickness of a thermally grown silicon oxide dielectric layer but with an additional layer of silicon nitride high-K dielectric material to provide performance, reliability and manufacturability.
The present invention employs materials and methods which are known in the art of microelectronics fabrication, but in a novel order and sequence. Therefore the present invention is readily commercially implemented.